1. Field of the Invention
The present invention relates generally to automatic verification of transmission margins of various types of transmission lines transmitting signals such as high-speed digital signals, and more particularly, to a transmission margin verification apparatus, method and program using a combination of existing measuring devices to effect the automatic verification.
2. Description of the Related Art
The transmission speed of a digital signal in digital electronic equipment is becoming faster in recent years against the backdrop of the increased amount of information processed that is demanded of such equipment. This is the reason why the verification of a transmission margin is required in transmission lines transmitting high-speed digital signals.
While the transmission margin verification in a transmission line has been conducted through theoretical calculations based on the specification of each of the components in the transmission line and the general transmission engineering theories, the verification results thereof have fallen short of constituting grounds to guarantee the product performance because of many errors.
Patent documents are available in relation to such transmission lines and transmission margins thereof, namely, Japanese Patent Application Laid-Open Publication Nos. 1993-276039, 1999-232314 and 2002-245107. Japanese Patent Application Laid-Open Publication No. 1993-276039 does little more than disclose an anti-malfunction A/D conversion apparatus with a shorter conversion time to solve the problem that if the A/D conversion starts with an external trigger from an external trigger input terminal that is also used as an analog input terminal, those signals input as external trigger signals rather than as analog signals are also subjected to an A/D conversion, that this conversion creates a one-channel time loss until the A/D conversion is complete, and that this gives rise to a one-channel delay in the generation of an interrupt signal.
Japanese Patent Application Laid-Open Publication No. 1999-232314 discloses, as a high-frequency circuit design support apparatus, a configuration having a correction data generation unit and operable to convert coordinate variations of the parts in the state diagram in the state diagram display unit to parameter variations of the symbols in the corresponding circuit diagram.
On the other hand, Japanese Patent Application Laid-Open Publication No. 2002-245107 relates to high-frequency circuit design and high-frequency measurement and discloses the determination of parameters in an impedance matching circuit provided at the input and output ends of a high-frequency semiconductor device.
Incidentally, a transmission margin of a transmission line is unacceptable as grounds to guarantee the product performance if the verification of the margin is not appropriate. Such a problem is not disclosed at all in Japanese Patent Application Laid-Open Publication Nos. 1993-276039, 1999-232314 and 2002-245107, and the technology to solve the problem is neither disclosed nor suggested.